Peter Vertlib is a Senior Design Verification Engineer who currently works at Intel, focusing on Core Architecture verification. They have extensive experience with e language (Specman) and Verilog, operating in a Unix environment while utilizing Git. Previously, Peter held the role of Design Verification Engineer at Qualcomm from 2020 to 2021 and served as a Verification Engineer at Intel Corporation from 2016 to 2020. Peter earned a Bachelor of Science in Industrial Electronics Technology from Ort Braude College in 2016 and completed a practical engineering program in Electrical and Electronics Engineering at Braude Academic College from 2005 to 2007.
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