Raj Shingala is a Staff Engineer at Marvell Technology, specializing in design verification with expertise in various protocols such as PCIe and UFS. Previously, Raj held multiple roles at Cadence Design Systems, including Lead R&D Engineer, where they contributed to the development of PCIe and UniPro specifications and was awarded a US Patent for verifying a cross-connection of lanes. Raj earned a Master of Technology in Microelectronics from BITS Pilani and a Bachelor of Technology in Electronics and Communication Engineering from Dharmsinh Desai University.
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