Ruby Li

Ruby Li has extensive experience as an ASIC Design Engineer at Marvell, starting in August 2010 and continuing to the present. Responsibilities include designing and implementing RTL blocks, writing design specifications, collaborating with design verification teams, and creating test cases for RTL verification. Additionally, Ruby develops block-level synthesis flows using Synopsys Design Compiler and Cadence Genus, writing synthesis scripts, reviewing synthesis reports, and addressing synthesis errors and timing violations. Prior to Marvell, Ruby served as an ASIC Design Intern at Broadcom from July 2009 to August 2010.