Sameer Vaidya

Sameer Vaidya serves as a Senior Director of Validation Engineering at Marvell Technology since April 2020, overseeing Application Engineering teams across Santa Clara, Longmont, and Shanghai. Responsibilities include the bring-up and silicon validation of R&D and production chips, as well as formulating test methodologies. Prior experience at Marvell Semiconductor from 2003 to 2013 encompasses roles such as Engineering Manager and Staff Engineer, where Sameer allocated resources and developed a recruitment process, and held leadership positions in chip validation and systems application engineering, contributing significantly to the development of validation platforms and application notes. Earlier experience at Micron Semiconductors involved working in DRAM R&D, focusing on advanced technologies and failure analysis. Sameer Vaidya holds a Master of Science in Electrical Engineering from Clemson University and a Bachelor of Engineering in Electrical Engineering from Savitribai Phule Pune University.