Stephen Potvin

Principal Timing Engineer

Stephen Potvin is currently a lead design engineer at Marvell Technology, bringing 14 years of experience in designing control systems for next-generation DRAM designs, including DDR5 and LPDDR4. They have developed expertise in various aspects of high-quality DRAM systems, from initial architecture to silicon debug, ensuring successful system testing with minimal changes. Stephen previously held a design engineer position at Nanya Technology after completing a Bachelor of Science in Electrical and Electronics Engineering from Clarkson University.

Location

Burlington, United States

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