Wei Liu

Wei Liu is an accomplished architect at 燧原科技, specializing in various technologies including Verilog/VHDL and FPGA debug. With a career that began in 2003, they served as a Senior ASIC Engineer at Magima, focusing on IP design and verification, and later contributed to Pixelworks in the same capacity from 2009 to 2011. Wei has been a Senior Staff Engineer and Manager at Marvell since 2011, where they lead critical projects such as the APB subsystem and eMMC/SD host controller. Their expertise also encompasses design management from their time at Synopsys Inc from 2017 to 2019.