MP

Miteshwar Patel

Silicon DFT Engineer

Miteshwar Patel has extensive experience in the semiconductor industry, having worked in various roles at eInfochips (An Arrow Company) from May 2019 to October 2021, including positions as Senior DFT Engineer Level - 1 and Level - 2, DFT Engineer, and Project Trainee. Miteshwar then advanced to Juniper Networks, serving as ASIC Engineer Staff and subsequently ASIC Engineer Sr. Staff from July 2023 to June 2025. Currently, Miteshwar holds the position of Silicon DFT Engineer at MatX since June 2025. Miteshwar's academic background includes a Master's degree in Technology from Ganpat University (2011-2013) and a Bachelor's degree from S.V.M.I.T. (2007-2011), as well as foundational education at Ankur School (1999-2007).

Location

San Jose, United States

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