Arijit Saha

Arijit Saha is a Senior RTL Design Engineer at MaxLinear, where they have been contributing since 2022. Previously, Arijit gained valuable experience as a DFT Intern at STMicroelectronics from 2021 to 2022. They earned a Master of Technology (MTech) in VLSI Design from the Vellore Institute of Technology in 2022, and earlier completed their HS(+2 Stage) in Science at Udaipur Ramesh HS School in 2013. Additionally, Arijit is pursuing their Madhyamik Examination at Vivekananda Vidyapith High School.