Jayakrishna V

Jayakrishna V is a Senior RFIC Layout Design Group Lead with over 15 years of extensive experience in the semiconductor industry. Jayakrishna has held various roles at MaxLinear, including Senior RFIC Layout Design Engineer and Senior Staff RFIC Layout Engineer, from 2014 to 2021, and has progressed to leadership positions such as RFIC Layout Design Group Lead. Prior to their time at MaxLinear, Jayakrishna worked as a Senior Analog Layout Design Engineer at Cadence Design Systems and as an Analog Layout Designer at Cosmic Circuits. Jayakrishna earned a B-Tech in Electronics from St. An's College of Engineering & Technology, completing the degree in 2009.