Jitesh Sanghavi is a Senior ASIC Verification Manager with 19 years of experience in ASIC/IC verification, specializing in diverse verification methodologies and processes. They currently lead verification projects at MaxLinear and previously held significant roles at Qualcomm, Cadence Design Systems, and Insilica Semiconductors. Jitesh has demonstrated expertise in verification planning, architecting test benches, and a variety of protocols including Ethernet and PCIe. They are pursuing a Bachelor's degree in Engineering from Mumbai University.
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