Sandeep Bengeri is a Staff RFIC Layout Designer at MaxLinear, with over seven years of experience in analog layout engineering. They have worked with various FinFET nodes, including 7nm, 10nm, 14nm, and 16nm, and have experience in LDMOS technology nodes tsmc80 and tscm40. Previously, Sandeep held positions as an Analog Layout Engineer at Synaptics Incorporated and Sankalp Semiconductor, contributing to various analog blocks and IO layouts. They hold a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from GIT Belgaum, completed in 2016. Sandeep is known for their strong leadership and management skills, having successfully led a team of five.
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