Senthilvelu P J is a seasoned engineer with extensive experience in design automation and infrastructure, currently serving as a Senior Staff Design Automation and Infrastructure Engineer at MaxLinear since 2022. They previously held prominent roles at Microchip Technology Inc. as a Principal CAD Engineer and at PMC-Sierra as a Staff CAD Infrastructure Engineer from 2011 to 2018. Prior to that, Senthilvelu worked at Info Innovative Technologies and Wipro Technologies as a Design Engineer and RTL Design Engineer, respectively. They hold a Bachelor of Engineering in Electronics and Communication from Adhiparasakthi Engineering College, an M.Tech in VLSI Design from Vellore Institute of Technology, and an MBA in Technology Management from Anna University.
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