Vijetranayak Mudkavi is an experienced RTL Design Engineer with 7 years in ASIC development, microarchitecture, and digital design. Currently a Senior Design Engineer at MaxLinear, they have previously worked as a Consultant at Microchip Technology Inc. and as an RTL Design Engineer at Frenus Tech Pvt. Ltd., contributing significantly to projects in networking, memory subsystems, and high-speed data processing. Vijetranayak is pursuing a Bachelor of Engineering in Electronics and Communications Engineering at MVJ College of Engineering. Passionate about semiconductor advancements, they focus on developing efficient digital solutions that push technological boundaries.
This person is not in any teams
This person is not in any offices