Yashaswini Kumar

Yashaswini Kumar is a Senior ASIC Design Verification Engineer at MaxLinear, bringing over three years of experience in IP, Subsystem, and SoC-level verification using UVM and SystemVerilog. They have authored test plans, executed constrained-random verification, and managed regressions while achieving significant code and functional coverage. Yashaswini has also developed C-based verification environments and engaged in Python-based post-silicon design validation testing. They completed their Bachelor of Engineering in Electronic and Communications Engineering from Vidyavardhaka College of Engineering and is currently pursuing a Master of Technology in VLSI Design at the Indian Institute of Technology Jammu.