Aju Narayanan is a Senior Design Verification Engineer at MediaTek, where they leverage expertise in design verification using UVM and SystemVerilog. Aju holds a Master of Engineering in Embedded Systems from BITS Pilani and previously worked as a Software Engineer at VVDN Technologies, focusing on camera image quality tuning. Aju's academic background and professional experience drive their commitment to robust verification processes and innovation in technology solutions.
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