David Lin

David Lin is a Senior Design Verification Engineer at MediaTek, where they are enhancing their design verification skills in SystemVerilog, UVM, and Formal methods. Previously, David worked at 遠傳電信 as an Engineer focused on presales and project management. David gained valuable experience at 聯發科技, initially as a Design Verification Engineer (Dispatch) and later as a regular Design Verification Engineer. David earned a Bachelor's degree in Electrical Engineering from 中原大學 and a Master's degree from 國立臺灣科技大學.