Dheeraj Bhaskar is a Staff Engineer at MediaTek, having previously served as a Senior Silicon Design Engineer at AMD from 2022 to 2025, where they contributed to DDR5/LPDDR5 and GDDR6 Memory PHY development in advanced process nodes. Before that, as a Member of Technical Staff at Rambus from 2019 to 2021, Dheeraj focused on high-speed SerDes PHY design. Dheeraj earned a B.Tech in Electronics and Communication from the College of Engineering, Trivandrum, and a M.Tech in Electronic Systems Engineering from the Indian Institute of Science.
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