Divya Sethi

Divya Sethi is a Senior Engineer at MediaTek since October 2019, specializing in Static Timing Analysis (STA) and synthesis. Prior to this role, Divya worked as an Internship Trainee at RV-VLSI VLSI and Embedded Systems Design Center from February 2019 to August 2019, focusing on block-level physical design flow and interpreting timing reports. Divya holds a Master of Technology in VLSI Design from the Centre for Development of Advanced Computing (C-DAC), Mohali (2014-2016), a Bachelor of Technology in Electronics and Communication Engineering from Malout Institute of Management and Information Technology (2010-2013), and a Diploma in Electronics and Communication Engineering from Govt. Polytechnic for Women, Sirsa (2007-2010).