Harini SR is currently a Staff DFT Engineer at MediaTek, where they have worked on successful tape outs for 5nm and 4nm technologies. Previously, they held the positions of Senior DFT Engineer and DFT Engineer at MediaTek, contributing to DRC cleanup, pattern generation, and post-silicon debugging. Harini also served as an Assistant Professor at Dhole Patil College of Engineering from 2016 to 2017 and interned at IISc, Bangalore, focusing on FPGA-based system development for indoor air quality monitoring. Harini is pursuing an MTech in Digital Electronics at Visvesvaraya Technological University.
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