Jerin Varghese

Jerin Varghese is a VLSI DFT Engineer with extensive experience in design for test methodologies, including scan insertion and ATPG for complex SoCs. They have worked as a DFT Engineer at AMD and Synapse Design Inc. before becoming a Senior DFT Engineer at MediaTek. Jerin holds a Bachelor of Technology in Electronics and Communications Engineering from Mahatma Gandhi University, completed in 2015. Proficient in industry-standard tools and scripting, they focus on enhancing test coverage and silicon quality.