Jiahui Lim

Jiahui Lim is an experienced engineer currently serving as a Staff Engineer at MediaTek since October 2020, where responsibilities include whole chip timing closure and the development of in-house utilities for TECO/STA, as well as acting as APR Block Owner for approximately 2-3 million instances. Previously, Jiahui held the position of SoC Physical Design Engineer, focusing on static timing analysis, timing closure, and hierarchical checks while also developing in-house utilities. Jiahui's internship at Intel Corporation in 2019 as a PSV Engineer involved VLSI design, logic synthesis, and static timing analysis. Jiahui holds a Master of Engineering in Microelectronics and Computer Systems from Universiti Teknologi Malaysia, completed in March 2023, and a Bachelor's degree in Biomedical Engineering from the same institution, awarded in 2020, along with STPM in Science from Maktab Sultan Abu Bakar in 2015.