Liam Cheng is a Sr. Digital Design Engineer at 聯發科, promoted in May 2023, with expertise in DRAMC/EMI integration, RTL synthesis, DFT, STA timing closure, and physical design for advanced technology node projects. Liam possesses strong schedule-oriented PPA skills, including logic synthesis and physical-aware design. Previously, as a Semiconductor Component Engineer at Cisco, Liam improved ASIC yield by 5% QoQ and reduced RMA returns by 35% using data analytics. Early career experience as an R&D Device Engineer at United Microelectronics Corporation involved BCD platform development and device design. Liam holds a Master's degree in Electronics Engineering from National Chiao Tung University and a Bachelor's degree in Physics from National Central University.
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