Manish Pillai is currently a Senior Design Engineer specializing in Static Timing Analysis (STA) at MediaTek, where they contribute to advanced physical design projects. Previously, Manish worked as an RTL Design Engineer at Tech Mahindra Cerium and completed a student internship at Indian Oil Corp Limited, focusing on software development for an RTU system. Manish is pursuing an MTech in VLSI Design at Vellore Institute of Technology, combining academic excellence with practical experience to drive innovation in the semiconductor industry.
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