Pomin Wang

Pomin Wang is an experienced design verification, emulation, and digital design engineer with a strong background in electronic engineering. Pomin held positions at Ralink Technology as a Design Verification Engineer, and at ITRI as a Digital Design Engineer, where they focused on ASIC/FPGA design and communication systems. They worked at Cadence Design Systems as a Principal Application Engineer and Lead Application Engineer, specializing in design verification and simulation acceleration. Currently, Pomin is a Senior Technical Manager in Design Verification at MediaTek, where they continue to influence the field. Pomin earned a Master's degree in Electrical and Electronics Engineering and an Executive MBA from National Taiwan University, along with a Bachelor's degree in the same field from National Central University.