禮宏 闕 is currently an Analog/Serdes Technical Manager at MediaTek, specializing in high-speed SerDes interfaces with MIPI M/C/D-PHY. Since 2021, they have been a key contributor to the development of innovative PAM4 technology and serve as the system planner for various complex algorithms. Prior to this role, they gained extensive experience as a Senior Analog/Serdes IC Design Engineer at MediaTek from 2014 to 2021, where they led efforts in MIPI CPHY and DPHY technology, achieving significant speed improvements. 禮宏 holds a Master's degree in Analog IC design and a Bachelor's degree in Electrical Engineering from National Taiwan University.
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