Rajeev Pandey is currently an Analog Design Engineer at MediaTek in Taiwan, specializing in the design of ultralow-power analog circuits and systems for biomedical and IoT applications. Rajeev earned a Ph.D. in Electrical and Computer Engineering from National Yang Ming Chiao Tung University and a Master's degree in Integrated Electronics and Circuits from the Indian Institute of Technology Delhi. Their research includes the design of a robust analog front-end for continuous monitoring of PPG signals, resulting in several published papers in prestigious journals. Prior to MediaTek, Rajeev served as a research assistant at National Chiao Tung University, focusing on various analog circuit design projects.
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