SIMIN JIANG

Simin Jiang is a seasoned staff engineer at 联发科技 since April 2014, specializing in chip design and implementation using tools such as ICC, ICC2, and Innovus. With previous experience as a PR engineer at Alchip and GLOBALFOUNDRIES, Simin has a strong background in backend design and physical synthesis, notably in L3Cache and chip-level designs, including timing budgeting and power planning. Early career experience at the National High Performance IC Design Center involved critical SRAM design and optimization for high-speed applications. Simin holds a Master's degree in Micro-electronics from Zhejiang University.