Srikanth Vaggu is an experienced RTL Design Engineer currently employed at MediaTek since January 2022, where the focus includes RTL design, verification, and synthesis of SoC Top IP I/O Pinmux, utilizing advanced process nodes. Previous roles at MediaTek include Senior Engineer and Synthesis & STA Engineer, with contributions to a flagship smartphone SoC's 5G modem development. Srikanth also served as an Intern, gaining insights into synthesis processes and EDA tools. Academic credentials include a Master of Engineering in Microelectronics from BITS Pilani, Hyderabad Campus, and a Bachelor of Technology in Electronics and Communication Engineering from Anurag Group of Institutions. Additional experience encompasses roles as a Teaching Assistant at BITS Pilani and an Associate System Engineer at IBM.
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