Steven Tseng

Steven Tseng is a Senior Technical Manager at MediaTek, with experience since July 2019 focused on N4 GPU implementation, PnR flow development, and improvements in CPU/GPU PnR PPA. Previously, Steven worked as a Physical Design CAD Engineer at Apple from May 2017 to July 2019, where the focus was on top-level physical hierarchical implementation flow development. Prior to that, as a Principal Customer Engagement Engineer at Cadence Design Systems from October 2013 to May 2017, Steven led the physical implementation of a quad-core Cortex-A53 CPU project at 28nm and developed an automated flow for performance and leakage goals. Steven's earlier role as Technical Manager at MediaTek involved creating low-power SOC design methodologies that enabled rapid implementation at the 28nm process node. Steven holds a Master's degree in Electronic Design Automation from National Tsing Hua University and a Bachelor's degree in Computer Science from Fujen Catholic University, supplemented by advanced studies at Udacity.