Tzu-hsien Yang is a Technical Manager at 聯發科, specializing in memory circuit design and verification. Previously, Tzu-hsien worked as a Senior Design Engineer at 台積電 from 2017 to 2021, where they contributed to the N5 MRAM project by enhancing write performance and improving power efficiency. Tzu-hsien also interned at 台積電, winning first place in the 2016 summer intern competition for their high-speed read scheme design for N28 MRAM. Tzu-hsien holds a master's degree in Electrical Engineering from National Tsing Hua University, completed in 2017.
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