Vidhan Jolly is an experienced Analog Mixed-Signal Design Engineer currently working at MediaTek since February 2023, focusing on High-Speed 224G SerDes Links. Prior experience includes a Design Engineer Intern position at Silicon Labs where the focus was on analog mixed-signal design for low-power IoT MCUs, and an Analog Design Engineer role at MediaTek involving analog mixed-signal design for CPU processors using advanced FinFET technology nodes. Vidhan Jolly also worked at Texas Instruments as an Analog Design Engineer in the Analog Power Products team, specializing in voltage references and supervisors, and previously completed an internship in analog validation. Educational qualifications include a Master of Science in Electrical and Computer Engineering from Texas A&M University and a Bachelor of Engineering in Electrical and Electronics Engineering from the Birla Institute of Technology and Science, Pilani.
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