Vinyas J Shetty is a Senior Engineer at MediaTek, where they continue to excel in ASIC design flow from RTL to GDSII. Previously, Vinyas held the position of Engineer at the same company from 2021 to 2025, showcasing their expertise in floorplanning, power planning, and static timing analysis. Vinyas completed an Advanced Diploma in ASIC Design - Physical Design at RV-VLSI Design Center in 2019 and earned a Bachelor of Engineering in Electrical, Electronic, and Communications Engineering from Dayananda Sagar College of Engineering in 2018.
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