Vivek R. is a Senior Staff RFIC Design Engineer at MediaTek, leading the development of front-end components for FR1 mobile handsets. Previously, they worked at Analog Devices in Ireland, where they designed a 40GHz buffer in 22nm FDSOI. They earned a Master of Science in Electrical Engineering from KU Leuven, specializing in electronics and IC, and completed their undergraduate studies in Instrumentation and Electronics Engineering at Jadavpur University. Additional experience includes an internship at Nokia Bell Labs and a role as a design engineer at Cadence Design Systems.
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