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Aarti Ramesh

ASIC Design Engineer

Aarti Ramesh is an experienced engineer with a strong background in physical design and ASIC development. Aarti has held various roles, including Technical Lead at Innovium Inc., and has worked as a Senior Engineer and Engineer at Qualcomm, focusing on high-speed Ethernet switch design and server SoC technologies. Aarti's expertise includes optimizing timing critical paths, custom floorplanning, and conducting dynamic circuit simulations, particularly with Spice. Currently, Aarti serves as an ASIC Design Engineer at Meta, specializing in the development of video and ML inference chips for data centers. Aarti holds a B.E. in Electrical and Electronics Engineering from the College of Engineering, Guindy, and an M.S. in Computer Engineering from Texas A&M University.

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