Binal Nasit has a strong background in electrical engineering with a Bachelor of Technology in Electronics & Telecommunication from the College of Engineering Pune and a Master of Science in Electrical Engineering (VLSI Design) from the University of Southern California. Experience includes mentoring at the USC Ming Hsieh Institute, serving as a Technology Analyst at Credit Suisse, and working as an IP Logic Design Engineer at Intel Corporation, focusing on logic design of CXL IP for multiple generations. Currently, Binal serves as an ASIC Design Engineer at Meta, contributing to advanced chip design initiatives.
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