Darpana Pendyala

Darpana Pendyala is an experienced ASIC Implementation Engineer at Meta since October 2025, with prior roles including Senior Staff Timing Design Engineer at Marvell Technology and Senior Timing Design Engineer at Qualcomm. At Qualcomm, Darpana led DDRPHY timing closure across advanced technology nodes, managed timing sign-off, and collaborated with international teams to ensure project alignment. Previous experience includes serving as an Analog Design Engineer at Intel, where Darpana focused on qualitative analysis of custom libraries and developed regression workflows. Darpana began the career with a Master's degree in Electrical and Computer Engineering from the University of Massachusetts Amherst and a Bachelor's degree in Technology from Jawaharlal Nehru Technological University.