Dejan Vulevic is a seasoned professional in design verification, currently serving as a Design Verification Manager at Meta since February 2019. Vulevic has previously held significant roles, including Senior Manager and Manager of Design Verification at Intel Corporation from March 2016 to February 2019, and Manager of Design Verification at Altera from January 2014 to December 2015. Earlier experience includes positions as Team Lead - SoC Design Verification - Multimedia and Project Leader - UHS2PHY at Texas Instruments - Elsys Eastern Europe from November 2009 to May 2012, as well as Sr Design Verification Engineer at Qualcomm - Encore Semi from October 2012 to December 2013. Vulevic's extensive background reflects a strong expertise in design verification across multiple leading technology companies.
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