Hsin Ling Lu is an experienced engineer with expertise in digital design and ASIC engineering. Recently completed an internship as a Digital Design Engineer at 恩智浦半導體, where significant contributions included revising IC designs for Type-C devices, managing inputs and outputs across analog blocks, and automating verification processes using Python, achieving a notable efficiency increase. Currently serving as an ASIC Design Engineer at Meta, Hsin Ling Lu is pursuing a Master of Science in Electrical and Computer Engineering at 密西根大學, building on a foundational education from 國立臺灣大學.
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