Jinjin Jinjin is an experienced engineering professional with a strong background in semiconductor design and development. Starting as a Research Assistant at Fudan University, Jinjin contributed to WLAN baseband design and Bluetooth modem design, along with FPGA implementations. Academic achievements include a Ph.D. from Oregon State University, focusing on VLSI architecture design. At Marvell Semiconductor, Jinjin served as a Staff Design Engineer, leading flash controller IP architecture and firmware development. Progressing to ScaleFlux, Jinjin took on senior roles, including Design Manager and Senior Design Manager, overseeing core IP design and managing project execution. Currently, Jinjin Jinjin is an ASIC Design Engineer at Meta, specializing in AI Infra chip design.
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