J++ Liang is an experienced engineering professional with a focus on ASIC design verification. Liang has held various roles throughout a distinguished career, including positions at Intel Corporation as an ASIC Design Verification Engineer, Qualcomm as an ASIC Design Verification Manager, and AMD where roles included ASIC Post-Silicon Validation Lead and ASIC Design Verification Lead. Liang has also contributed as an ASIC Verification/Diagnostics Engineer at Sun Microsystems, Software Engineer at Computer Graphics Systems Development Corp., and Software Consultant at PictureTalk, Inc. Currently, Liang is employed as a Design Verification Engineer at Meta, following a tenure as a Senior Design Verification Engineer at Amazon Lab126.