Laurent Y. has a background in VLSI and design verification, with a Bachelor of Applied Science in Computer Engineering from Simon Fraser University. Starting as a VLSI Intern at Linear Technology from May 2012 to June 2013, Laurent subsequently worked at Teradici as a Verification Engineer from June 2013 to March 2015, utilizing UVM methodologies for verification tasks. Afterward, Laurent held the position of SoC Design Verification Engineer at Intel Corporation from March 2015 to October 2021, where contributions included architectural pathfinding and leading a verification team. Currently, Laurent serves as a Design Verification Engineer at Meta since November 2021, focusing on ASIC development for advanced AR, VR, and XR silicon products, and delivering critical support for New Technology Initiatives.
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