Medha P. has a strong background in electrical engineering, holding a Bachelor of Technology and Master of Technology from the Indian Institute of Technology, Roorkee, and a Master of Science from the University of Wisconsin-Madison. Professional experience includes roles as a Senior Engineer at Qualcomm from July 2017 to August 2020, a Pixel IP Performance Modeling Intern and Performance Modeling Engineer at Apple in 2021, and currently serving as an ASIC Architecture and Modeling engineer at Meta since May 2024. Additionally, Medha P. completed an internship at Eaton Corporation in 2016, focusing on designing a Switched Mode Power Supply for an ultra-wide input range.
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