Michael Hatley possesses extensive experience in hardware design and digital engineering, having worked at several prominent technology companies. As a Senior Hardware Design Engineer at Microsoft from April 2019 to August 2022, Michael contributed to RTL design and microarchitecture for various ASIC and FPGA projects, including the development of a Late Stage Reprojection C++ model for augmented reality applications. Following this role, Rivos Inc. employed Michael as a Member of Technical Staff from August 2022 to December 2023. Currently, Michael serves as an ASIC Design Engineer at Meta since February 2024, focusing on advanced semiconductor design. Prior to these roles, Michael was a Senior Digital Design Engineer at NXP Semiconductors from June 2015 to November 2018, specializing in high-speed and low-power designs for diverse applications. Michael's career began with an internship at National Instruments in 2014, working on VHDL development for digitizers and oscilloscopes. Michael earned a Bachelor of Science in Electrical Engineering from Texas Tech University in 2015.
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