Pallavi Kinnera

Pallavi Kinnera is a Silicon PD Engineer at Meta since November 2021, focusing on driving execution for complex, high-performance SoC designs for Reality Labs AR/VR products. Prior to this role, Pallavi worked at Intel Intelligent Fabric from June 2017 to November 2021 as a Physical Design Engineer in the Barefoot Division of the Data Platforms Group, and as a PD CAD Methodology Engineer, delivering production PnR ECO flows and enabling project-specific manual ECOs. Earlier experience includes an internship at Intel Corporation as a Physical Design CAD Engineer, where Pallavi developed health checks for design rule violations and enhanced floorplan generation features. Educational qualifications include a Credential of Readiness from Harvard Business School Online, a Master’s in Electrical and Computer Engineering from Georgia Institute of Technology, and a Bachelor of Technology in Electronics and Communications Engineering from SRM IST Chennai.