Prasad Pandit

Prasad Pandit is an experienced engineer specializing in FPGA design and ASIC engineering, currently working at Meta as an ASIC Engineer since October 2023. Previously, Prasad held roles as a Senior Design Verification Engineer at Cirrus Logic and as a Design Verification Engineer at Qualcomm, focusing on next-generation WiFi verification using UVM methodologies. Early career experiences include positions at Atria Logic Inc. and Maven Silicon, where skills in RTL design, verification, and project management were developed. Prasad has also served as a Graduate Teaching Assistant at Portland State University, aiding in courses related to microprocessor interfacing. Educational qualifications include a Master's Degree in Electrical and Computer Engineering from Portland State University and a Bachelor's Degree in Electronics Engineering from G.H. Raisoni College of Engineering.