Romil Savla is an experienced ASIC Design Verification Engineer currently employed at Meta since November 2024. Prior to this role, Romil worked at Apple as a Design Verification Engineer from September 2016 to November 2024, and held similar positions at NXP Semiconductors and Freescale Semiconductor. At NXP, Romil contributed to the verification of advanced processors and developed infrastructure for high-end digital networking projects. At Freescale, Romil was instrumental in verifying next-generation multi-threaded processors and developing comprehensive verification plans and testbench infrastructure. Romil's educational background includes a Master of Science in Electrical Engineering from the University of Southern California and a Bachelor of Engineering in Electronics from the University of Mumbai.
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