Sheetal Raghu

Sheetal Raghu is an experienced engineer with a strong background in physical design. At Intel Corporation, Sheetal held the position of Physical Design Engineer from March 2016 to April 2025, followed by the role of ASIC Physical Design Engineer at Meta since April 2025. Prior to this, Sheetal completed a Master's Degree in Electrical and Computer Engineering at the University of Cincinnati, achieving a perfect GPA of 4.0, and worked as a student focusing on advanced algorithms and power optimization. Sheetal's earlier experience includes serving as a Scientist/Engineer at the Indian Space Research Organisation from September 2009 to March 2014, where contributions included the design of control systems and software tuning for telemetry missions. An academic foundation was established with a Bachelor's degree in Electronics and Telecommunication from the College of Engineering, Trivandrum, graduating with a GPA of 8.28/10.