Sriram Muthukumar is an experienced ASIC Design Engineering Manager at Meta since March 2025, with a rich background in semiconductor design and engineering. Prior to this role, Sriram worked at Altera from June 2005 to January 2008, where positions included Advanced Design Engineer, Senior Design Engineer, and Micro Architect & RTL Design Lead. From February 2012 to October 2021, Sriram was associated with Intel Labs, serving as RTL Design Lead & Engineering Manager and Component Design Engineer within the silicon prototyping group in India. Sriram holds a Bachelor of Engineering degree in Electronics & Communications from Bharathiar University and a Master's degree from Clemson University.
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