Sumanth Batchu

Sumanth Batchu is an experienced engineer with a strong background in logic design and FPGA development. From June 2015 to December 2022, Sumanth worked as a Logic Design Engineer at Marvell Semiconductor, contributing to the design, synthesis, and validation processes on five projects, while honing skills in RTL design and verification using Verilog, VHDL, and System Verilog. Additionally, Sumanth gained hands-on experience with lab debugging tools such as logic analyzers and oscilloscopes. Currently, Sumanth is an ASIC Engineer intern at Meta since December 2022. Sumanth holds a Master of Science in Electrical Engineering from Arizona State University and a Bachelor of Technology in Electronics and Communication Engineering from JNTU Kakinada.