Teja Kala

Teja Kala has extensive experience in the semiconductor industry, holding positions as a Pre-Silicon Verification Engineer at Intel Corporation from March 2017 to June 2020 and as an ASIC Solutions Intern at NVIDIA for a brief period in early 2016, where significant contributions included chip bring-up and functional testing for NVIDIA Pascal GPUs. Currently employed as an ASIC Engineer in Design Verification at Meta since June 2020, Teja has demonstrated proficiency in FPGA design verification and DFMEA in previous roles, including a Controls Hardware Intern at Lennox International. Teja holds a Bachelor's Degree in Electrical and Electronics Engineering from the National Institute of Technology Calicut and a Master's Degree in Electrical Engineering from Texas A&M University, achieving a GPA of 3.9.